1. Technical Field
The present invention relates to liquid crystal display panels adopting the horizontal electric field mode and, more particularly, to a liquid crystal display panel employing the fringe field switching (which will be hereinafter termed “FFS”) mode, for which a high aperture ratio and low power consumption can be achieved by appropriately forming each storage capacitor included therein.
2. Field of Invention
Liquid crystal display panels, which are characterized by lightness in weight, small thickness and low power consumption as compared with cathode-ray tubes (CRTs), have been used for various types of electrical devices as displays incorporated therein. A principle for displaying images employed in such a liquid crystal display panel is such that, an amount of transmitted light or an amount of reflected light varies in accordance with alignment direction changes of individual liquid crystal molecules in proportion to the intensity of an electric field applied to the liquid crystal molecules, each of which is initially aligned in a prescribed direction resulting from a rubbing process performed on alignment films having the liquid crystal molecules interposed therebetween.
There are two modes in methods of applying an electric field to a liquid crystal layer included in a liquid crystal display, one being a vertical electric field mode, the other one being a horizontal electric field mode. In a liquid crystal display panel adopting the vertical electric field mode, an electric field, which is generated by a pair of electrodes having a liquid crystal layer interposed therebetween and extends in a direction substantially vertical relative to the pair of electrodes, is applied to liquid crystal molecules included in the liquid crystal layer. For liquid crystal displays adopting the vertical electric field mode, various modes, such as a twisted nematic (TN) mode, a vertical alignment (VA) mode and a multi-domain vertical alignment (MVA), are well known to those skilled in the art. In a liquid crystal display panel adopting the horizontal electric field mode, an electric field, which is generated by a pair of electrodes being formed in a mutually insulated condition at the inside side of one of the pair of substrates having a liquid crystal layer interposed therebetween and extends in a direction substantially horizontal relative to the pair of electrodes, is applied to liquid crystal molecules included in the liquid crystal layer. For the liquid crystal display panels adopting the horizontal electric field mode, an in-plane switching (IPS) mode, in which the pair of electrodes are formed so as not to be overlapped in plan view, and a fringe field switching (FFS) mode, in which the pair of electrodes are formed so as to be overlapped in plan view, are well known to those skilled in the art.
Among these liquid crystal display panels employing various modes, a liquid crystal display panel employing the FFS mode includes a plurality of pairs of an upper electrode and a lower electrode having an insulating film interposed therebetween, the upper electrode and the lower electrode being located on different layers, respectively, and further, the upper electrode includes slit-shaped apertures therein, through which an electric field extending in a substantially horizontal direction is applied to the liquid crystal layer. Such liquid crystal display panels employing the FFS mode have advantages of a large viewing angle and improved image contrast, and thus, nowadays, are in widespread use. Hereinafter, a configuration of a liquid crystal display panel employing the FFS mode disclosed in JP-A-2002-90781 will be described with reference to FIGS. 7 and 8.
FIG. 7 is a schematic plan view illustrating a one-pixel area of an array substrate included in a liquid crystal display panel employing the FFS mode, which is disclosed in JP-A-2002-90781. FIG. 8 is a schematic sectional view taken along the line VIII-VIII of FIG. 7.
A liquid crystal display panel 50 shown in FIGS. 7 and 8 includes an array substrate AR and a color filtering substrate (not shown in figures). In the array substrate AR, a plurality of scanning lines 52 and common wiring 53 are formed on the surface of a transparent substrate 51 so as to be parallel with each other, and further, in a direction orthogonal to the extension directions of the scanning lines 52 and the common wiring 53, a plurality of signal lines 54 are formed. Moreover, each lower electrode 55, which is composed of a transparent conductive material, such as indium tin oxide (ITO), and is connected to the common wiring 53, is formed so as to cover one of areas partitioned by the scanning lines 52 and the signal lines 54, and further, on a gate insulating film 56 and a passivation film 57 covering the surface of the lower electrode 55, upper electrodes 59 each being composed of a transparent material, such as an ITO, and having a plurality of stripe-shaped slits 58 are formed. Further, surfaces of the upper electrodes 59 and the plurality of slits 58 are coated by an alignment film (not shown in figures).
Moreover, a thin film transistor (TFT) operating as a switching element is formed adjacent to a position at which one of the scanning lines 52 and one of the signal lines 54 intersect each other. With respect to the TFT, a semiconductor layer 61 is formed on the gate insulating film 56 covering the surface of the scanning lines 52, and a portion of the signal lines 54, extending so as to partially cover the surface of the semiconductor layer 61, constitutes a source electrode S of the TFT, and a portion of the scanning lines 52, being located below the semiconductor layer 61, constitutes a gate electrode G of the TFT, and further, a portion of the upper electrode 59, overlapping a part of the semiconductor layer 61, constitutes a drain electrode D of the TFT. Further, the upper electrode 59 is electrically connected to the drain electrode D through a contact hole 62, which is formed in the passivation film 57.
Further, the color filtering substrate, which is omitted from being illustrated, includes a color filter layer, an overcoat layer and an alignment film on a transparent substrate included therein. Moreover, further configurations, which allow, firstly, the array substrate AR and the color filtering substrate to be located so as to be opposite each other so that each pair of an upper electrode and the corresponding lower electrode included in the array substrate AR is opposite to a specific portion of the color filter layer included in the color filtering substrate, secondly, the liquid crystal layer to be shielded between the array substrate and the color filtering substrate, and thirdly, two polarization plates to be located outside the array substrate and the color filtering substrate, respectively, so that polarization directions thereof are orthogonal to each other, enables realization of the liquid crystal display panel 50 employing the FFS mode. In this liquid crystal display panel 50 employing the FFS mode, each upper electrode 59 and the corresponding lower electrode 55 are configured to be located so as to be opposite each other and have the gate insulating film 56 and the passivation film 57 interposed therebetween, and as a result, a capacitance is generated between each upper electrode 59 and the corresponding lower electrode 55. Accordingly, the liquid crystal display panel 50 employing the FFS mode, in which the whole of each pixel area is allowed to operate as a storage capacitor, does not particularly require formation of a storage capacitance in the pixel area, and as a result, has an advantage in that an aperture ratio is increased to a greater degree than in the case of existing liquid crystal panels adopting the vertical electric field mode for which formation of each storage capacitance is particularly required.
However, in a liquid crystal display panel employing the FFS mode, in the case where each storage capacitance is formed by an upper electrode, a lower electrode and an insulating film interposed therebetween, the storage capacitance formed in a pixel area increases in proportion to the dimensions of the pixel area. In liquid crystal display panels having a low degree of fineness which is, for example, approximately 100 pixel per inch (ppi), the dimensions of the pixel area become large, and thus, the storage capacitance becomes large in proportion thereto, and further, so as to supply each pixel with sufficient charge, the size of each TFT is required to be large, and this TFT of large size adversely results in reducing of an aperture ratio. Furthermore, in proportion to increasing the amount of charge stored in each pixel, an amount of power consumed in the liquid crystal display panel is likely to increase.